View S3F380D_8713498.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

s3c380d/f380d product overview 1- 1 1 product overview overview samsung s3c380d 16/32 -bit risc microcontroller is a cost -effective and high-performance microcontroller solution for tv applications . a mong the outstanding feature s of the s3c380d is its cpu core, a 16/32 -bit risc processor ( arm7tdmi ) designed by advanced risc machines, ltd. the arm7 tdmi core is a low-power, general-purpose microprocessor macro-cell that was developed for use in application-specific and customer-specific integrated circuits. its simple, elegant, and fully static design is particularly suitable for cost-sensitive and power-sensitive applications. the s3c380d was developed using the arm7 tdmi core, cmos standard cell, and a data path compiler. most of the on-chip function blocks were designed using an hdl synthesizer. the s3c380d has been fully verified in the samsung asic test environment. by providing a complete set of common system peripherals, the s3c380d minimizes overall system costs and eliminates the need to configure additional components. the integrated on-chip functions that are described in this document include: ? 4-kbyte ram (3008-byte (1504 16 bits) general register and 1088-byte (544 16 bits) osd/ccd ram) ? 128-kbyte internal program memory ? two 14-b it pwm modules ? three 16-bit timers ? on screen display module ? crystal/ceramic oscillator or external clock can be used as the clock source ? standby mode support: sleep mode ? one 8-bit basic timer and 3-bit watchdog timer ? interrupt controller (16 interrupt sources and 2 vectors) ? five 4-bit adcs ? four p rogrammable i/o ports ? 42-pin sdip
product overview s3c380d/f380d 1- 2 features cpu ? arm7t cpu core memory ? 4-kbyte ram (3008-byte general purpose register area + 1088-byte osd/ccd ram) ? 128 kbyte internal program memory general i/o ? four i/o ports (25 pins total) (6 v o/d: 3 pins, 5 v o/d: 4 pins) basic timer and watchdog timer ? 8-bit counter + 3-bit counter ? overflow signal of 8-bit counter makes a basic timer interrupt and control the oscillation warm-up time ? overflow signal of 3-bit counter makes a system reset timer/counters ? three general purpose 16-bit timer/counters with interval timer modes interrupts ? 16 interrupt sources and 2 vectors ? fast interrupt processing ? 2 interrupt shadow registers (32 bit 2) pulse width modulation (pwm) module ? 14-bit pwm with 2-channel pwm counter a/d converter ? 5 - channel: 4-bit conversion resolution (flash adc) remocon receiver ? fifo 8 steps ? fifo interrupt is full (8) step overflow on screen display (osd) mode ? analog level osd ? halftone ? 64 character colors ? 16 different character sizes ? graphic osd ? s/w ccd oscillator frequency ? 32,768 hz external crystal oscillator ? 1 hz generation for real time clock ? pll (phase lock loop) controlled oscillators ? maximum 16 mhz cpu clock operating temperature range ? - 20 c to + 85 c operating voltage range ? 4.5 v to 5.5 v package type ? 42 -pin sdip
s3c380d/f380d product overview 1- 3 block diagram int0-int3 p0.0-p0.7 p1.0-p1.7 p2.0-p2.7 arm7tdmi 16-bit risc cpu core ram 3008 byte rom 128 kbyte watchdog timer 16-bit timer/counter 2 ext. interrupt irin remocon receive 16-bit timer/counter 1 16-bit timer/counter 0 osd & ccd system control & pll v dd , v ss x in x out reset lpf port0 port1 port2 p3.0 port3 pwm0 pwm1 14-bit pwm adc0-adc4 4-bit adc osd/ccd ram 1088 byte figure 1-1. s3c380d block diagram
product overview s3c380d/f380d 1- 4 pin assignments p0.0/pwm0 p0.1/pwm1 p0.2 p1.0 p1.1 p1.2 p1.3 p1.4/adc1 p1.5/adc2 p1.6/adc3 p1.7/adc4 v dd1 v ss1 p2.0/int0 p2.1/int1 p2.2/int2 p2.3/int3 p2.4 p2.5 p2.6 p2.7/osdht s3c380d (42-sdip-600) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p0.3 p0.4 p0.5 p0.6 p0.7 v ss2 v pp p3.0 v dd2 v ss x out v s s v ss3 lpf cvi in (adc0) v-sync h-sync vblank vred vgreen vblue 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1-2. s3c380d pin assignments (42-sdip)
s3c380d/f380d product overview 1- 5 pin descriptions table 1 - 1. s3c380d pin descriptions pin name pin type pin description circuit type pin numbers share pins p0.0 i/o input mode or push-pull output mode is software configurable. p0.0: pwm0 (14-bit pwm output) 6 1 pwm0 p0.1-p0.2 p0.3 general i/o port (3-bit), input or n-channel open-drain output is software configurable. pins can withstand up to 6-volt loads. an alternative function is supported. p0.1: pwm1 (14-bit pwm output) 3 2-3 42 pwm1 p0.4-p0.7 general i/o port (4-bit), input or output mode (push-pull or n-channel open drain) is software configurable. 7 38-41 p1.0-p1.3 i/o input/output mode or push-pull output mode is software configurable. 6 4-7 p1.4-p1.7 general i/o port (4-bit), configurable for digital input or n-channel open drain output. p1.4-p1.7 can withstand up to 5-volt loads. multiplexed for alternative use as external inputs adc1-adc4. 4 8-11 adc1- adc4 p2.0-p2.3 i/o general i/o port (4-bit), input or push-pull output mode is software configurable. multiplexed for alternative use as external interrupt inputs int0-int3. 2 14-17 int0-int3 p2.4-p2.7 i/o input mode or push-pull output mode is software configurable. an alternative function is supported. p2.7: osdht (halftone signal output) 6 18-21 osdht p3.0 i/o input mode or push-pull output mode is software configurable. 6 35 pwm0 o output pin for 14-bit pwm0 circuit 6 1 p0.0 pwm1 o output pin for 14-bit pwm1 circuit 3 2 p0.1 adc1-4 i input for 4-bit resolution flash a/d converter 4 8-11 p1.4-7 int0-int3 i external interrupt input pins 2 14-17 p2.0-3 osdht o halftone control signal output for osd 6 21 p2.7 irin i remocon signal input normal mode: remocon signal input otp write mode: v pp =12.5 v 1 36 ? cvi in i video signal input 8 28 adc0
product overview s3c380d/f380d 1- 6 table 1 - 1. s3c380d pin descriptions (continued) pin name pin type pin description circuit type pin numbers share pins reset i system reset input pin 9 33 ? lpf ? pll filter pin ? 29 ? h-sync i h-sync input for osd and ccd 1 26 ? v-sync i v-sync input for osd and ccd 1 27 ? v blank o video blank signal output for osd and ccd 5 25 ? v red o red signal output for osd and ccd 5 24 ? v green o green signal output for osd and ccd 5 23 ? v blue o blue signal output for osd and ccd 5 22 ? adc0 i input for 4-bit resolution flash a/d converter (1.5v-2.0v) 8 28 cvi in v dd1 , v dd2 v ss1 , v ss2 v ss3 ? power supply pins ? 12, 34 13, 37 30 ? x in , x out i, o system clock pins (32,768 hz) ? 31,32 ?
s3c380d/f380d product overview 1- 7 pin circuits in noise filter schmitt trigger input figure 1-3. pin circuit type 1 (h-sync, v-sync, irin) v dd in/out output disable data noise filter schmitt trigger input input int figure 1-4. pin circuit type 2 (p2.0-p2.3, int0-int3)
product overview s3c380d/f380d 1- 8 schmitt trigger input in/out note: circuit type 3 can withstand up to 6 v loads. input data figure 1-5. pin circuit type 3 (p0.1-p0.3, pwm1) schmitt trigger input in/out note: circuit type 4 can withstand up to 5 v loads. data input a/d in figure 1-6. pin circuit type 4 (p1.4-p1.7, adc1-adc4)
s3c380d/f380d product overview 1- 9 v dd data in/out figure 1-7. pin circuit type 5 (v blue , v green , v red , v blank ) v dd in/out output disable data input schmitt trigger input figure 1-8. pin circuit type 6 (p0.0, p1.0-p1.3, p2.4-p2.7, p3.0, osdht, pwm0)
product overview s3c380d/f380d 1- 10 v dd data open-drain in/out input schmitt trigger input output disable figure 1-9. pin circuit type 7 (p0.4-p0.7) a/d input in figure 1-10. pin circuit type 8 (cvi in, adc0) schmitt trigger input in v dd 50 k w noise filter figure 1-11. pin circuit type 9 ( reset )
s3c380d/f380d product overview 1- 11 cpu core overview the s3c380d cpu core is the arm7tdmi processor, a general purpose, 32-bit microprocessor developed by advanced risc machines, ltd. (arm). the core's architecture is based on reduced instruction set computer (risc) principles. the risc architecture makes the instruction set and its related decoding mechanisms simpler and more efficient than with microprogrammed complex instruction set computer (cisc) systems. the resulting benefit is high instruction throughput and impressive real-time interrupt response. pipelining is also employed so that all components of the processing and memory systems can operate continuously. the arm7tdmi has a 32 -bit address bus. an important feature of the arm7tdmi processor, differentiating it from the arm7 processor, is a unique architectural strategy called thumb . the thumb strategy is an extension of the basic arm architecture and consists of 36 instruction formats. these formats are based on the standard 32-bit arm instruction set, but have been re-coded using 16-bit wide opcodes. because thumb instructions are one-half the bit width of normal arm instructions, they produce very high- density code. when a thumb instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent instruction in the standard arm instruction set. the arm core then processes the 16-bit instruction as it would a normal 32-bit instruction. in other words, the thumb architecture gives 16-bit systems a way to access the 32-bit performance of the arm core without incurring the full overhead of 32-bit processing. because the arm7tdmi core can execute both standard 32-bit arm instructions and 16-bit thumb instructions, it lets you mix routines of thumb instructions and arm code in the same address space. in this way, you can adjust code size and performance, routine by routine, to find the best programming solution for a specific application. instruction decoder and logic control address register address register register bank write data register multiplexer barrel shifter 32-bit alu instruction pipeline and read data register figure 1-12. arm7tdmi core block diagram
product overview s3c380d/f380d 1- 12 instruction set the s3c380d instruction set is divided into two subsets: a standard 32-bit arm instruction set and a 16-bit thumb instruction set . the 32-bit arm instruction set is comprised of thirteen basic instruction types which can, in turn, be divided into four broad classes: four types of branch instructions which control program execution flow, instruction privilege levels, and switching between arm code and thumb code. three types of data processing instructions which use the on-chip alu, barrel shifter, and multiplier to perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths). three types of load and store instructions which control data transfer between memory locations and the registers. one type is optimized for flexible addressing, another for rapid context switching, and the third for swapping data. three types of co-processor instructions which are dedicated to controlling external co-processors. these instructions extend the off-chip functionality of the instruction set in an open and uniform way. note all 32-bit arm instructions can be executed conditionally. the 16-bit thumb instruction set contains 36 instruction formats drawn from the standard 32-bit arm instruction set. the thumb instructions can be divided into four functional groups: four branch instructions. twelve data processing instructions, which are a subset of the standard arm data processing instructions. eight load and store register instructions. four load and store multiple instructions. note each 16-bit thumb instruction has a corresponding 32-bit arm instruction with the identical processing model. the 32-bit arm instruction set and the 16-bit thumb instruction sets are good targets for compilers of many different high -level lang uages. when assembly code is required for critical code segments, the arm programming technique is straightforward, unlike that of some risc processors which depend on sophisticated compiler technology to manage complicated instruction interdependencies. pipelining is employed so that all parts of the processor and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
s3c380d/f380d product overview 1- 13 operating states from a programmer's point of view, the arm7tdmi core is always in one of two operating states. these states, which can be switched by software or by exception processing, are: arm state (when executing 32-bit, word-aligned, arm instructions), and thumb state (when executing 16-bit, half-word aligned thumb instructions). operating modes the arm7tdmi core supports seven operating modes: user mode : the normal program execution state fiq (fast interrupt request) mode : for supporting a specific data transfer or channel process irq (interrupt request) mode : for general purpose interrupt handling supervisor mode : a protected mode for the operating system abort mode : entered when a data or instruction pre-fetch is aborted system mode : a privileged user mode for the operating system undefined mode : entered when an undefined instruction is executed operating mode changes can be controlled by software, or they can be caused by external interrupts or exception processing. most application programs execute in user mode. privileged modes (that is, all modes other than user mode) are entered to service interrupts or exceptions, or to access protected resources.
product overview s3c380d/f380d 1- 14 registers the s3c380d cpu core has a total of 37 registers: 31 general-purpose, 32-bit registers, and 6 status registers. not all of these registers are always available. which registers are available to the programmer at any given time depends on the current processor operating state and mode. note when the s3c380d is operating in arm state, 16 general registers and one or two status registers can be accessed at any time. in privileged mode, mode-specific banked registers are switched in. two register sets, or banks, can also be accessed, depending on the core's current state: the arm state register set and the thumb state register set : the arm state register set contains 16 directly accessible registers: r0-r15. all of these registers, except for r15, are for general-purpose use, and can hold either data or address values. an additional (seventeenth) register, the cpsr (current program status register), is used to store status information. the thumb state register set is a subset of the arm state set. you can access eight general registers, r0- r7, as well as the program counter (pc), a stack pointer register (sp), a link register (lr), and the cpsr. each privileged mode has a corresponding banked stack pointer, link register, and saved process status register (spsr). the thumb state registers are related to the arm state registers as follows: thumb state r0-r7 registers and arm state r0-r7 registers are identical thumb state cpsr and spsrs and arm state cpsr and spsrs are identical thumb state sp, lr, and pc map directly to arm state registers r13, r14, and r15, respectively in thumb state, registers r8-r15 are not part of the standard register set. however, you can access them for assembly language programming and use them for fast temporary storage, if necessary.
s3c380d/f380d product overview 1- 15 exceptions an exception arises whenever the normal flow of program execution is interrupted. for example, when processing must be diverted to handle an interrupt from a peripheral. the processor's state just prior to handling the exception must be preserved so that the program flow can be resumed when the exception routine is completed. multiple exceptions may arise simultaneously. to process exceptions, the s3c380d uses the banked core registers to save the current state. the old pc value and the cpsr contents are copied into the appropriate r14 (lr) and spsr register. the pc and mode bits in the cpsr are forced to a value which corresponds to the type of exception being processed. the s3c380d core supports seven types of exceptions. each exception has a fixed priority and a corresponding privileged processor mode, as shown in table 1-2. table 1-2. s3c380d cpu exceptions exception mode on entry priority reset supervisor mode 1 (highest) data abort abort mode 2 fiq fiq mode 3 irq irq mode 4 prefetch abort abort mode 5 undefined instruction undefined mode 6 (lowest) software interrupt supervisor mode 6 (lowest)
s3c380d/f380d electrical data 17- 1 17 electrical data overview this chapter describes the s3c380d electrical data. information is presented according to the following table of contents: table 17-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to + 7.0 v input voltage v i1 p0.1-p0.3, p1.4-p1.7 (open-drain) ? 0.3 to + 6 v v i2 all ports except v i1 ? 0.3 to v dd + 0.3 output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 10 ma all i/o pins active ? 50 output current low i ol one i/o pin active + 20 ma total pin current for ports 0, 1, 2, and 3 + 100 operating temperature t a ? ? 20 to + 85 c storage temperature t stg ? ? 40 to + 125 c
electrical data s3c 380d/f380d 17- 2 table 17-2. d.c. electrical characteristics (t a = ? 20 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit input high v ih1 all input pins except v lh2 0.8 v dd ? v dd v voltage v ih2 reset 0.85 v dd input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v v il2 reset 0.15 v dd output high voltage v oh1 v blank , p2.4, p2.5 i oh = ? 1 ma v dd ? 1.0 ? ? v v oh2 all ports except v oh1 i oh = ? 500 ua v dd ? 0.5 output low voltage v ol1 p2.4, p2.5 i ol = 15 ma ? ? 1.0 v v ol2 all ports except v ol1 , v ol3 i ol = 2 ma 0.4 v ol3 v blank i ol = 1 ma 0.4 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 1 ua i lih2 v in = v dd x in , x out 3 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? ? 1 ua i lil2 v in = 0 v x in , x out ? 3 ?- 20 output high leakage current i loh1 v out = v dd all output pins except i loh2 ? ? 1 ua i loh2 v out = 6 v p0.1-p0.3, p1.4-p1.7 (n-channel, open-drain) 10 output low leakage current i lol v out = 0 v all output pins ? ? ? 1 ua
s3c380d/f380d electrical data 17- 3 table 17-2. d.c. electrical characteristics (continued) (t a = - 40 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit pull-up resistor r p2 v in = 0 v reset only 30 50 70 k w supply current i dd1 v dd = 5 v 16 mhz cpu clock ? 50 100 ma i dd2 sleep mode 0.5 1 table 17-3. a.c. electrical characteristics (t a = - 40 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth, t intl ports 2.0-2.3 ? 300 ? ns reset input low width t rsl input ? 1000 ? ns v-sync pulse width t vw ? 4 ? ? m s h-sync pulse width t hw ? 3 ? ? m s noise filter t nf1 p2.0-p2.3 ? 300 ? ns t nf4 glitch filter (oscillator block) 1000 t nf3 reset 1000 t nf2 h-sync, v-sync 300 t intl t rsl t inth 0.8 v dd 0.2 v dd figure 17-1. input timing measurement points
electrical data s3c 380d/f380d 17- 4 table 17-4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 17-5. data retention supply voltage in sleep mode (t a = ? 20 c to + 85 c, v dd = 4.5 v to 5.5 v) parameter symbol conditions min typ max unit data retention supply voltage v dddr sleep mode 2 ? ? v data retention supply current i dddr sleep mode v dddr = 5.0 v ? ? 2 ma execution of sleep operation reset occurs ~ ~ v dddr ~ ~ sleep mode oscillation stabilization time normal operting mode data retention mode t wait reset v dd figure 17-2. sleep mode release timing when initiated by reset
s3c380d/f380d electrical data 17- 5 table 17-6. oscillator frequency (t a = ? 20 c + 85 c) oscillator clock circuit test condition min typ max unit crystal or ceramic s3c380d x in x out c1 c2 v dd = 4.5 v to 5.5 v c1 = c2 = 33 pf recommended ? 32,768 ? hz external clock s3c380d x in x out v dd = 4.5 v to 5.5 v ? 32,768 ? hz table 17-7. oscillator clock stabilization time (t a = ? 20 c + 85 c, v dd = 4.5 v to 5.5 v) oscillator test condition min typ max unit crystal x in = 32,768 hz ? ? 20 ms external clock x in input high and low level width (t xh, t xl ) 15 ? 125 ns oscillator t wait when released by a reset, x in = 32,768 hz ? ? 500 ms stabilization time t wait when released by a interrupt (note) ? ? 4 ms note: the duration of the oscillator stabilization time, t wait, when it is released by an interrupt, is determined by the settings in the basic timer control register, btcon.
electrical data s3c 380d/f380d 17- 6 table 17-8. a/d converter electrical characteristics (t a = - 20 c to + 85 c, v dd = 4.5 v to 5.5 v (adc1-adc4), v dd = 5.0 v (adc0)) parameter symbol conditions min typ max unit resolution ? ? ? ? 4 bit absolute accuracy (1) ? cpu clock = 16 mhz adc0 ? ? 1.0 lsb adc1-4 ? ? 0.5 lsb conversion time (2) t con cpu clock = 16 mhz ? (3) ? ns analog input voltage v ian ? adc1-4 av ss ? av ref v adc0 1.5 ? 2.0 v analog input impedance r an ? 2 ? ? m w analog output impedance r oan cpu clock = 16 mhz conversion time = 4 mhz ? ? 5 k w cpu clock = 16 mhz conversion time = 0.5, 1, and 2 mhz ? ? 10 k w notes: 1. excluding quantization error, absolute accuracy values are within 1 lsb (adc0), 0.5 lsb (adc1-4) 2. ?conversion time? is the time required from the moment a conversion operation starts until it ends 3. adc conversion time is controled by adcon.9-.8.
s3c380d/f380d mechanical data 18- 1 18 mechanical data overview the s3c380d microcontroller is currently available in 42-pin sdip (42-sdip-600) package. note : dimensions are in millimeters. 39.50 max 39.10 0 .2 0.50 0.1 1.778 (1.77) 0.51 min 3.30 0.3 3.50 0.2 5.08 max 42-sdip-600 0-15 1.00 0.1 0.25 + 0.1 - 0.05 15.24 14.00 0 .2 #42 #22 #21 #1 figure 18-1. 42-pin sdip package dimensions
s3c380d/f380d S3F380D mtp 19- 1 19 S3F380D mtp overview the S3F380D single-chip cmos microcontroller is the mtp (multiple time programmable) version of the s3c380d microcontroller. it has an on-chip flash rom instead of a masked rom. the flash rom is accessed by serial data format. the S3F380D is fully compatible with the s3c380d, both in function and pin configuration. p0.0/pwm0 p0.1/pwm1 sclk /p0.2 sdat /p1.0 p1.1 p1.2 p1.3 p1.4/adc1 p1.5/adc2 p1.6/adc3 p1.7/adc4 v dd /v dd1 v ss /v ss1 p2.0/int0 p2.1/int1 p2.2/int2 p2.3/int3 p2.4 p2.5 p2.6 p2.7/osdht S3F380D (42-sdip-600) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 p0.3 p0.4 p0.5 p0.6 p0.7 v ss2 / v ss irin/ v pp p3.0 v dd2 / v dd reset/ reset x out x in v ss3 / v ss lpf cvi in (adc0) v-sync h-sync vblank vred vgreen vblue 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 19-1. S3F380D pin assignment (42-sdip)
S3F380D mtp s3c380d/f380d 19- 2 table 19-1. descriptions of pins used to read/write the flash rom (S3F380D) main chip during programming pin name pin name pin no. i/o function p1.0 (pin 4) sdat 4 i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p0.2 (pin 3) sclk 3 i/o serial clock pin (input only pin) irin v pp 36 i 0-5 v: operating mode 12.5 v: mtp mode reset reset 33 i 5 v: operating mode, 0 v: mtp mode v dd /v ss v dd /v ss 12/34, 13/30/37 i logic power supply pin. table 19-2. comparison of S3F380D and s3c380d features characteristic S3F380D s3c380d program memory 128-kbyte flash rom 128-kbyte mask rom operating voltage (v dd ) 4.5 v to 5.5 v 4.5 v to 5.5 v mtp programming mode v dd = 5 v, v pp = 12.5 v ? pin configuration 42 sdip 42 sdip flash rom programmability user program under 100 time programmed at the factory

▲Up To Search▲

Price & Availability of S3F380D

	To Download S3F380D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .